During the transmission of low data rates, impedance matching between the driver and the line is generally not usual or frequently not necessary. In this case, frequently only simple inverter circuits are used; cf. first circuit arrangement according to the PRIOR ART illustrated as an example by reference to FIG. 2A.
The known circuit arrangement according to FIG. 2A has an output node (=single-ended); the transistor (in FIG. 2A, that is the upper) allocated to the voltage source SQ comprises a p-channel transistor, the transistor (in FIG. 2A, that is the lower) allocated to the reference potential (=for example, earth potential or zero potential or ground) comprises an n-channel transistor.
In order to transmit high data rates with low error, the impedance of the output stage or output impedance Zout of line driver is typically matched to the line input impedance ZL (matching: ZOut=ZL=for example, fifty Ohms). As a result of such impedance matching, signal reflections are absorbed which would otherwise adversely affect the quality of the transmission signal.
Furthermore, high data rates are frequently transmitted as differential signals in order to minimize interference; examples of this are LVDS (=Low Voltage Differential Signaling), SLVS (=Scalable Low Voltage Signaling), differential ECL (=Emitter Coupled Logic), differential LVPECL (=Low Voltage Positive Emitter Coupled Logic) or similar.
In these differential circuits there is no longer only one output node (=so-called single-ended arrangement) but a differential output stage.
This means that interference with respect to the reference potential, for example, with respect to the earth potential or with respect to the zero potential or with respect to ground no longer have an effect since such interference is mutually compensated by forming a difference in the two output signals; cf. differential circuit arrangements according to the PRIOR ART illustrated as an example by reference to FIG. 2B, FIG. 2C, FIG. 2D.
In FIG. 2B, the voltage source SQ (idealised, having a negligible impedance) delivers about 1.2 Volt; the two load resistances each of fifty Ohms as an example (in each case, with respect to the reference potential, for example, with respect to the earth potential or with respect to the zero potential or with respect to ground) serve as output impedance so that about one hundred Ohms in total lies between Out + and Out −; the input signal at In − has a phase shift of 180 degrees with respect to the input signal at In +.
If the gate voltage VG1 at the first n-channel transistor T1 [the gate connection of T1 is assigned to the first input connection In +] is smaller than the sum of the source voltage VS1 and the transistor threshold voltage VthN [the source connection of T1 is constant current source KQ (idealized having a negligible impedance) and is assigned to the source connection of the second n-channel transistor T2], the n-channel transistor T1 has a high resistance and is in the off-state; accordingly, this first n-channel transistor T1 opens and conducts if the gate voltage VG1 at this first n-channel transistor T1 is higher than the sum of the source voltage VS1 and the transistor threshold voltage VthN.
The differential circuit arrangement in FIG. 2B implements a changeover switch which allows a hard switching, wherein in each case one of the two load resistance nodes is pulled downwards. A disadvantage of the differential circuit arrangement according to FIG. 2B, however, is in particular the very low power efficiency due to a current efficiency of only about 25 percent, that is only about 25 percent of the current taken from the supply voltage source SQ flows in the data line to be driven. In order to achieve the desired current amplitude on the data line, four times as much current must be taken from the supply voltage.
In FIG. 2C the voltage source SQ (idealized having a negligible impedance) delivers about 2.5 Volt; whereas the two transistors T2 and T4 comprise n-channel transistors, the two transistors T1 and T3 are each a p-channel transistor which has a high resistance and is in the off-state when the gate voltage VG3 [the gate connection of T1 is assigned to the first input connection In +; the gate connection of T3 is assigned to the second input connection In −] is higher than the sum of the source voltage VS3 and the transistor threshold voltage VthP [the source connection of T1 or of T3 is assigned to the voltage source SQ]; accordingly, the p-channel transistor T1 or T3 opens as result of negligible resistance when the gate voltage at T1 or T3 is smaller than the sum of the source voltage VS3 and the transistor threshold voltage VthP.
However, a disadvantage of the differential circuit arrangement according to FIG. 2C linking to the inverter circuit from FIG. 2A in terms of principle is in particular the low power efficiency of only about fifty percent, that is the supply current taken from the voltage supply is about twice as high as the available output current.
In FIG. 2D the two load resistances each of fifty Ohms for example have a terminating function (in practice the two load resistances are each only about 47 Ohms since the transistors have a low residual resistance of about three Ohms in each case so that the differential circuit arrangement according to FIG. 2D has inadequacies in regard to the precision of the termination).
In fact, the differential circuit arrangement according to FIG. 2D has a very high power efficiency (current efficiency: almost one hundred percent); one particular disadvantage of the differential circuit arrangement according to FIG. 2D however is that impedance mismatches occur during the switching phases.
In this context, it should be considered that in order to minimize interference at the usually high data rates at which the differential signals are transmitted, the switching phases can account for about twenty percent up to about thirty percent of the entire time [ideal 0 and 1 pulses assumed in theory do not exist in reality, that is a slope rise or fall should be observed between the 0 state (off state) and the 1 state (on state)].
In other words, this means that the rise times and the fall times at high data rates are definitely relevant (and in the sense of the E[lectro]M[agnetic]C[ompatibility] even not completely undesired; in the case of ideal, that is infinitely steep slopes [negligible time difference], an [after Fourier transformation] infinitely high number of interference frequencies would appear.
If the gate voltage present at the p-channel transistor T1 and at the n-channel transistor T2 (simultaneously) falls, for example, from 1.2 Volt to 0 Volt, the p-channel transistor T1 does not yet respond until about the middle phase of the decreasing voltage, that is for example, at about 0.6 Volt whereas the n-channel transistor T2 is already beginning to turn off, that is, has a substantially increasing impedance, in the middle phase of the decreasing voltage, that is at 0.6 Volt for example. This results in a significantly increased output impedance during the switching slope, causing a deterioration in the reflection attenuation and the signal quality.